Verification of Scalable-Delay-Insensitive Asynchronous Circuits
نویسندگان
چکیده
The Scalable-Delay-Insensitive (SDI) model is proposed for high-performance asynchronous system design. In this paper, we focus on checking whether a circuit under SDI model satisfies some untimed properties, and formally show that checking these properties in the SDI model can be reduced to checking the same properties in the bounded delay model. This result suggests that the existing verification algorithms for the bounded delay model can be used for the verification of SDI circuits, which significantly helps the designers of SDI circuits. key words: formal verification, asynchronous circuits, SDI model, bounded delay model
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